This invention relates generally to metal silicide technology and to improved methods of forming integrated circuits.
Self - aligned refractory metal silicide technology is recognized as one of the keys to sustaining good device performance in integrated circuitry as device dimensions are scaled down. In particular, titanium disilicide (TiSi.sub.2) has become recognized as one of the most attractive metal silicides because of its low resistivity, stability and capability of self-aligned formation.
During the fabrication of high density integrated circuits the self-aligned silicidation process is generally performed after a polysilicon gate level has been patterned. This results in the formation of a highly conductive metallic silicide layer over all exposed areas of silicon, e.g., source/drain regions and polysilicon gates. As a result, source/drain diffusions can be made relatively shallow while maintaining acceptably low sheet resistance and the sheet resistance of polysilicon gates can also be minimized. Self-aligned processes for forming integrated circuits are well known in the art and are discussed at great length in U.S. Pat. No. 4,545,116 to Lau which is incorporated herein by reference.
In the past, manufacturing processes which utilize self-aligned silicide technology have required costly techniques to prevent formation of certain metallic oxides characterized by relatively high resistivity and poor etch selectivity relative to the silicide layer. By way of example, one of the most commonly used refractory metal silicides in the self-aligned process is titanium disilicide (TiSi.sub.2). An undesirable by-product which often results when titanium is reacted to form silicide is titanium dioxide (TiO.sub.2). TiO.sub.2 has an extremely high heat of formation and, being a very stable compound, is very difficult to remove. In fact, efforts to remove TiO.sub.2 from a circuit structure generally result in significant removal or degradation of the silicide layer.
TiO.sub.2 is known to result from competing reactions with gaseous oxygen during silicide formation. Even the presence of minor amounts of ambient oxygen, e.g., 2 parts per million, during the silicide reaction result in formation of significant amounts of TiO.sub.2. Common sources of oxygen include normal atmospheric contamination as well as the chemical break down of water vapor during the silicide reaction. In order to avoid oxygen contamination many IC manufacturing processes which incorporate silicide technology either utilize a noble gas such as argon to purge the oxygen or require that the silicide reaction be performed in a very low pressure, e.g., 0.45 Torr, environment. Because the purging process is costly and a low pressure ambient is difficult to maintain, it has been desirable to develop an environment insensitive silicide process which can be economically performed at atmospheric pressure.
Recently there has been disclosed a Capped Silicide Process wherein the problems of oxygen contamination are avoided by covering the metal layer with a cap material before performing the silicide reaction. In addition to preventing the formation of undesirable metallic oxides such as TiO.sub.2, the capped silicide process also prevents outdiffusion of underlying silicon when the silicide reaction is performed at temperatures above 600.degree. C. Techniques for performing self-aligned silicidation under oxide and nitride caps are discussed at great length in U.S. Pat. No. 4,690,730 and copending application Ser. No. 136,260, filed Dec. 22, 1987, each of which is assigned to the assignee of the present invention and is hereby incorporated by reference.
In certain applications of the Capped Silicide Process it is desirable, after forming silicide, to completely remove the cap material as well as portions of the metal layer which have not reacted to form silicide. For an oxide cap this has been accomplished with a two step etch, the first step involving a standard fluoro-etch chemistry, e.g., a combination of CHF.sub.3 and C.sub.2 F.sub.6, to anisotropically remove the cap material and the second step being a selective wet strip, e.g., H.sub.2 O.sub.2 /H.sub.2 SO.sub.4, or H.sub.2 O.sub.2 /NH.sub.4 OH with sonic agitation, to remove residual oxide and other nonsilicide material. The agitation is believed to aid in the undercutting of residual oxide and clearing out of undesirable conductive material along the sidewall filaments of polysilicon gates. This is believed to reduce the prevalence of electrical shorts between different moat regions.
With a silicon nitride cap, removal of cap material, as well as nonsilicided portions of the metal layer, has also been accomplished with a two step etch procedure. One known method comprises the step of applying a plasma etch, e.g., CF.sub.4 /O.sub.2, again followed by a selective wet strip. Because the CF.sub.4 /O.sub.2 plasma etch can be more isotropic than standard fluoro-etch chemistry, removal of nitride cap material along sidewall oxide filaments is believed to be more thorough than the removal of oxide cap material from similar locations. Thus sonic agitation may not be required during the nitride cap two step etch procedure.
While the above-described etch operations are capable of providing satisfactory results, it is preferred, particularly in a large scale manufacturing environment, to remove the cap material with a more isotropic etch process in order to more completely eliminate material which could contribute to formation of electrical shorts between different moat regions. The etch process should also be highly selective in order to avoid particulate problems associated with overetching and potential degradation of circuit elements.